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This research presents a design for a two-bit magnitude comparator utilizing various technologies including CCMOS (Conventional CMOS), TGL (Transmission Gate Logic), PTL (pass transistor logic), GDI (gate diffusion logic), and FinFET. By comparing FinFET with existing models, significant improvements in Power Delay Product (PDP) are observed. The FinFET-based comparator demonstrates superior performance in terms of power consumption, time delay, and transistor area. Utilizing Cadence Virtuoso, simulated waveforms depicting greater than, equal to, and less than scenarios are generated, highlighting the efficacy of FinFET technology in achieving greater control device efficiency and compactness. Comparing with CMOS, FinFET have more than 70% benefits for time delay and power consumption.

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Efficient Two-Bit Magnitude Comparator with Hybrid Logic Approach

  • 会议论文

  • 发表日期：

    2025年

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  • R. Sindhuja,
  • E. John Alex,
  • K. Niranjan Reddy

摘要

This research presents a design for a two-bit magnitude comparator utilizing various technologies including CCMOS (Conventional CMOS), TGL (Transmission Gate Logic), PTL (pass transistor logic), GDI (gate diffusion logic), and FinFET. By comparing FinFET with existing models, significant improvements in Power Delay Product (PDP) are observed. The FinFET-based comparator demonstrates superior performance in terms of power consumption, time delay, and transistor area. Utilizing Cadence Virtuoso, simulated waveforms depicting greater than, equal to, and less than scenarios are generated, highlighting the efficacy of FinFET technology in achieving greater control device efficiency and compactness. Comparing with CMOS, FinFET have more than 70% benefits for time delay and power consumption.