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In this paper, we present an on-chip cache design and integration for 8-bit MIPS processor. The cache that we adopt is a direct-mapped cache with 1 byte cache blocks. It has a size of 16 bytes and is used for both instructions and data. We apply a top-down design methodology, i.e. we start from the architecture level and go down to its layout, with testing on each level. To integrate the cache, MIPS Finite State Machine (FSM) is modified accordingly, which results in controller architecture modifications. Assembly code is also rewritten to test cache functionality by SystemVerilog simulation. Upon completing functionality verification, cache components are implemented and integrated into Electric, and then their testing methodology is explained in detail. In addition, design quality is tested using SPICE simulations.

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Enhancing MIPS Processor Efficiency with On-Chip Cache Integration

  • 会议论文

  • 发表日期：

    2025年

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  • Sreega Ramasubramanian,
  • Devi Charan Guduru,
  • Rajesh Krishnan,
  • P. Koushik

摘要

In this paper, we present an on-chip cache design and integration for 8-bit MIPS processor. The cache that we adopt is a direct-mapped cache with 1 byte cache blocks. It has a size of 16 bytes and is used for both instructions and data. We apply a top-down design methodology, i.e. we start from the architecture level and go down to its layout, with testing on each level. To integrate the cache, MIPS Finite State Machine (FSM) is modified accordingly, which results in controller architecture modifications. Assembly code is also rewritten to test cache functionality by SystemVerilog simulation. Upon completing functionality verification, cache components are implemented and integrated into Electric, and then their testing methodology is explained in detail. In addition, design quality is tested using SPICE simulations.