Comparators are the fundamental components in electronic systems, serving as key elements in various applications, such as voltage level detection, signal conditioning, and analog-to-digital conversion. In nearly all hardware sorters, a single, small, high-performance comparator core with a favourable cost–benefit ratio is crucial. Comparators are used in data convertors, digital communication devices, sorting methods, and processor address decoding units. This study suggests an area and power model of comparator. The proposed design is synthesized, functionally verified, and deployed using the Xilinx Vivado 2012.3. Curve fitting and regression in machine learning under supervised approach have been used in the model’s development. A comparator block with different I/O vector lengths is customized and tested against the power values obtained using Xpower Analyzer in Vivado.