Modern electronic appliances, including logic circuits and memory based devices, are being pushed to their limits by aggressive 2D scaling. However, it is inevitable that leakage will increase as generation of technology forward one to next. As a result, the demand for modelling leakage using various leakage reduction approaches has grown significantly, and the identification and simulation of various leakage contributing components has become a key aspect for estimating various leakage characteristics. In this research, researcher explores and then designs several circuits for self-controllable voltage levels (SVLs) in a 7 T SRAM cell organized in a 4 × 4 array. This method is a power-conserving model in which the supply voltage is at its highest during the active mode and at its lowest during the standby mode. The circuit has been simulated in cadence virtuoso using 45 nm technology at supply voltages of 1 V, 0.7 V, 0.5 V, and 0.3 V, with the results validated.