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In the dynamic landscape of Very Large-Scale Integration (VLSI) circuit design, the relentless pursuit of enhanced performance and fault tolerance confronts challenges arising from shrinking transistor sizes and heightened component density. This paper explores the integration of machine learning (ML) techniques into VLSI fault tolerance, in a new era of adaptability and resilience. Various ML-driven fault tolerance strategies are investigated, encompassing anomaly detection, supervised learning for fault classification, fault localization and diagnosis, reconfiguration and self-repair mechanisms, predictive maintenance, adaptive testing, and reliability modelling. By leveraging data-driven insights, these techniques promise to revolutionize VLSI circuit design, mitigating the impact of faults and setting the stage for future advancements.

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Machine Learning-Based Fault Tolerance Techniques for VLSI Circuit Design

  • 会议论文

  • 发表日期：

    2025年

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  • MJanga Reddy,
  • B. Satyanarayana,
  • M. Ravi,
  • Pokala Krishnaiah,
  • Chilukuri Dileep,
  • B. Annapoorna

摘要

In the dynamic landscape of Very Large-Scale Integration (VLSI) circuit design, the relentless pursuit of enhanced performance and fault tolerance confronts challenges arising from shrinking transistor sizes and heightened component density. This paper explores the integration of machine learning (ML) techniques into VLSI fault tolerance, in a new era of adaptability and resilience. Various ML-driven fault tolerance strategies are investigated, encompassing anomaly detection, supervised learning for fault classification, fault localization and diagnosis, reconfiguration and self-repair mechanisms, predictive maintenance, adaptive testing, and reliability modelling. By leveraging data-driven insights, these techniques promise to revolutionize VLSI circuit design, mitigating the impact of faults and setting the stage for future advancements.