This paper presents a comparison of different comparator architectures employed in Successive Approximation Register Analog-to-Digital Converters (SAR ADCs). It thoroughly examines and evaluates a spectrum of comparator designs, encompassing traditional architectures, double-tail comparator variations, and Elzakker comparator variations. All versions of comparator blocks were designed and prototyped in the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. This paper focuses on essential parameters such as power dissipation and propagation delay with varying supply voltage, aiming to highlight performance characteristics and trade-offs among different designs. In terms of static and dynamic power consumption, energy dissipation, and time delay, the Modified Elzakker Comparator emerges as a compelling choice, particularly suitable for applications prioritizing energy efficiency. Conversely, for applications emphasizing high-speed operation, the Modified Double-Tail Comparator proves to be a standout performer.