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In this paper, we present a millimetre-wave (MMW) low noise amplifier (LNA) with current reuse technique for defense covert warfare operations at 36 GHz. The systematic and analytically designed current reuse LNA consists of common Gate (CG) and Common Source (CS) amplifiers that are used to augment the gain. The proposed LNA is designed in gpdk 90 nm RF CMOS (complementary metal oxide semiconductor) technology that achieves peek gain (S21) of 25.6 dB, input return losses (S11) of −18.2 dB, Noise figure (NF) of 4.3 dB, reverse gain (S12) of −14.4 dB and output return losses (S22) of −12.14 dB at 36 GHz frequency. The developed Low Noise Amplifier (LNA) exhibits superior performance when compared to the previously described ones. The LNA current reuse topology for the performance analysis uses inductive - capacitive source degeneration. The simulations are done at 90 nm CMOS technology by using Cadence Virtuoso.

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A Millimetre-Wave LNA for Défense Covert Warfare Operations and Cybersecurity Applications

  • 会议论文

  • 发表日期：

    2025年

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  • Sarin Vijay Mythry,
  • P. Harsha Vardhini,
  • N. Dinesh Kumar,
  • B. Mennaiah,
  • Regonda Charan,
  • Kandikanti Bala Shiva Rama Krishna,
  • Penakanti Rajesh,
  • Bandari Vamshi

摘要

In this paper, we present a millimetre-wave (MMW) low noise amplifier (LNA) with current reuse technique for defense covert warfare operations at 36 GHz. The systematic and analytically designed current reuse LNA consists of common Gate (CG) and Common Source (CS) amplifiers that are used to augment the gain. The proposed LNA is designed in gpdk 90 nm RF CMOS (complementary metal oxide semiconductor) technology that achieves peek gain (S21) of 25.6 dB, input return losses (S11) of −18.2 dB, Noise figure (NF) of 4.3 dB, reverse gain (S12) of −14.4 dB and output return losses (S22) of −12.14 dB at 36 GHz frequency. The developed Low Noise Amplifier (LNA) exhibits superior performance when compared to the previously described ones. The LNA current reuse topology for the performance analysis uses inductive - capacitive source degeneration. The simulations are done at 90 nm CMOS technology by using Cadence Virtuoso.