The need for additional computational power for gaming, AI/ML, and video conferencing applications coupled with the ability to pack more transistors at lower geometries resulted in multi-core designs with 100s of identical cores packed in a SoC. Hierarchical test is a partitioned-test method designed to implement DFT and Test for these designs. This method eases computing resources and run times required for automatic test pattern generation (ATPG) on very large designs but poses unique challenges and opportunities for diagnosis. We discuss a generic diagnosis methodology for hierarchical test designs and propose a high throughput algorithm to increase the speed-up. Experiment results on industrial designs indicate no loss of diagnosis accuracy with the proposed approach and up to 15X speed-up is achieved using multiple device diagnostics mode.