This work presents the novel design of a 1-bit hybrid full adder based on Fin Field Effect Transistor-Transmission Gate Diffusion Input (FinFET-TGDI) technology, utilizing 21 transistors to achieve low Power Delay Product (PDP), which acts as the Figure of Merit (FOM) as its primary objective. To assess the performance of the proposed architecture, extensive simulations are conducted using the Cadence Virtuoso tool. The simulations are performed in an 18nm FinFET technology with a nominal supply voltage of 0.8V and ±10% variation and at a temperature of \(27^{\circ }{\text {C}}\) . The obtained results are then compared with existing state-of-the-art hybrid full adders documented in the literature. The results of the simulation show that the suggested design significantly outperforms the existing state-of-the-art adders in terms of power delay product (PDP), with improvements ranging from 10.19% to 60.76%. The performance parameters’ comparison of pre-layout and post-layout simulation for the proposed adder is also mentioned. Furthermore, the study comprehensively compares different process corner analyses to account for process variation in different hybrid full adders. Monte Carlo analysis is also done for the proposed adder architecture for realistic statistical distribution. Additionally, the study examines the variation in PDP with temperature across the range of \(-55\) to \(125\,^{\circ }{\text {C}}\) for all the mentioned adders.