A 0.076-MW 9.8-ENOB 1-MS/s SAR ADC Using Novel R-C Hybrid DAC
摘要
This study presents the development of a 10-bit differential-input SAR ADC with a 1-MS/s sampling rate, designed with the SCL 180-nm PDK. In order to reduce the power consumption and improve the performance of the ADC, a novel hybrid R-C DAC has been proposed, which employs R-2R and C-2C ladders for the 4-bit LSB and a binary-weighted capacitive array for the 6-bit MSB. This hybrid DAC architecture decreases the capacitor requirement by 84%, reducing the DAC area drastically while retaining good linearity. Additionally, a bootstrapped sample-and-hold circuit is introduced to lower harmonic distortion. The ADC exhibits an SNR of 61.06-dB, SFDR of 78.96-dB, and ENOB of 9.85-bits at near-Nyquist rate operation. Maximum INL/DNL are measured as 0.05/0.08-LSB. A dual power supply provides 0.9-V to the logic block and 1.8-V to the rest of the blocks to further reduce the logic switching energy. The ADC consumes 0.076-mW of power with a minimum FOM of 85.72-fJ/conversion.