Scholarlink

This article investigates the design, simulation, and performance assessment of three protection circuits, namely, Under Voltage Lockout (UVLO), Thermal Shutdown (TSD), and Current Foldback Circuit (CFC) for overload/short-circuit protection for a Low Dropout (LDO) regulator with a fully CMOS-based Bandgap Reference (BGR) circuit. The focus is on enhancing the lifespan and effectiveness of the regulator while safeguarding it from excessive loads and high temperatures. The TSD circuit, offering a hysteresis width of 14  \(^{\circ }\) C, maintains a maximum power dissipation of 1  \(\upmu \) W regardless of supply voltage fluctuations. The UVLO circuit permits regulator activation at a supply voltage of 1.24 V, consuming only 1.7  \(\upmu \) W. The CFC effectively limits the output current to 173.5 mA and foldbacks to 36.4 mA, with a power dissipation of just 7.7  \(\upmu \) W. Moreover, the regulator exhibits rapid transient response, transitioning in 1  \(\upmu \) s as the load fluctuates between 1mA and 80mA, within a supply voltage range of 1.7–2.2 V. The integrated system, comprising the regulator, bandgap reference (BGR) circuit, UVLO, TSD, and CFC, has a 41  \(\upmu \) A of maximum quiescent current ( \(I_q\) ). The system achieves overall efficiencies of 88% and 65% at input voltages of 1.7 V and 2.2 V, respectively.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design and Analysis of Low-Power Protection Circuits for LDO Regulators

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Arnab Deb,
  • David Selvakumar,
  • J. Mervin,
  • Anurupa Ghosh

摘要

This article investigates the design, simulation, and performance assessment of three protection circuits, namely, Under Voltage Lockout (UVLO), Thermal Shutdown (TSD), and Current Foldback Circuit (CFC) for overload/short-circuit protection for a Low Dropout (LDO) regulator with a fully CMOS-based Bandgap Reference (BGR) circuit. The focus is on enhancing the lifespan and effectiveness of the regulator while safeguarding it from excessive loads and high temperatures. The TSD circuit, offering a hysteresis width of 14  \(^{\circ }\) C, maintains a maximum power dissipation of 1  \(\upmu \) W regardless of supply voltage fluctuations. The UVLO circuit permits regulator activation at a supply voltage of 1.24 V, consuming only 1.7  \(\upmu \) W. The CFC effectively limits the output current to 173.5 mA and foldbacks to 36.4 mA, with a power dissipation of just 7.7  \(\upmu \) W. Moreover, the regulator exhibits rapid transient response, transitioning in 1  \(\upmu \) s as the load fluctuates between 1mA and 80mA, within a supply voltage range of 1.7–2.2 V. The integrated system, comprising the regulator, bandgap reference (BGR) circuit, UVLO, TSD, and CFC, has a 41  \(\upmu \) A of maximum quiescent current ( \(I_q\) ). The system achieves overall efficiencies of 88% and 65% at input voltages of 1.7 V and 2.2 V, respectively.