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The development of interfacing circuits for processing non-linear thermistor output signals in electro-optical payloads is required for accurate temperature measurements. This paper proposes a methodology to linearize the output signal of the thermistor. It significantly improves the thermistor linearity and reduces measurement error for the temperature range of −20  \(^{\circ }\) C to 60  \(^{\circ }\) C. The achieved correlation coefficient is \(\ge \) 0.99997, and the measurement error is <0.1 \(\%\) across all the corners. The circuit consists of a current biasing block to achieve constant current bias for the thermistor processing circuit. The reference bias has been designed without a complex bandgap reference circuit and achieves bias voltage stability of <200 ppm/ \(^{\circ }\) C for −55  \(^{\circ }\) C to 125  \(^{\circ }\) C. The design also includes the current trimming feature through an external resistor to cater to the requirements of different types of thermistors. The circuit has been designed using a 0.18  \(\upmu \) m CMOS process.

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High-Precision Programmable Thermistor Linearization ASIC for Electro-Optical Payload Applications

  • 会议论文

  • 发表日期：

    2025年

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  • Nishant Kumar,
  • Anuj Srivastava,
  • Namita Singh,
  • Hari Shankar Gupta

摘要

The development of interfacing circuits for processing non-linear thermistor output signals in electro-optical payloads is required for accurate temperature measurements. This paper proposes a methodology to linearize the output signal of the thermistor. It significantly improves the thermistor linearity and reduces measurement error for the temperature range of −20  \(^{\circ }\) C to 60  \(^{\circ }\) C. The achieved correlation coefficient is \(\ge \) 0.99997, and the measurement error is <0.1 \(\%\) across all the corners. The circuit consists of a current biasing block to achieve constant current bias for the thermistor processing circuit. The reference bias has been designed without a complex bandgap reference circuit and achieves bias voltage stability of <200 ppm/ \(^{\circ }\) C for −55  \(^{\circ }\) C to 125  \(^{\circ }\) C. The design also includes the current trimming feature through an external resistor to cater to the requirements of different types of thermistors. The circuit has been designed using a 0.18  \(\upmu \) m CMOS process.