This paper presents a capless low dropout regulator (LDO) utilizing a low-power Bandgap Reference (BGR) circuit and various low-power protection circuits: Under Voltage Lock Out (UVLO), Current Foldback Circuit (CFC), and Thermal Shutdown (TSD) circuit based on SCL 180 nm CMOS process. The proposed capless LDO ensures a stable output voltage of 1.5 V for input voltages ranging from 1.7 to 2.2 V, supporting a maximum load current of 80 mA with a low quiescent current and fast transient response. Simulation results demonstrate a load regulation of 0.011 mV/mA achieved by the LDO, attributed to its DC gain of 73 dB. The dropout voltage is limited to only 50 mV. In response to load changes, the LDO allows a maximum overshoot of 200 mV in the output voltage and achieves settling within 1 \(\upmu \) s. This transient performance is enabled by a transconductance amplifier and a push-pull output stage, which control the gate potential of the pass transistor. The load transient performance can also be attributed to the large gain bandwidth of 1.2 MHz and a phase margin of 67 \(^{\circ }\) . The regulator exhibits a PSRR of 75 dB @10Hz under a 80 mA load. The BGR circuit operates with a current consumption of 6 \(\upmu \) A, resulting in a maximum power dissipation of 13.2 \(\upmu \) W. The three low-power protection circuits (UVLO, TSD, and CFC) dissipate a maximum power of only 1.7 \(\upmu \) W, 1 \(\upmu \) W, and 7.7 \(\upmu \) W, respectively. The combined LDO, BGR circuit, and protection circuits maintain a maximum quiescent current \((I_q)\) of only 41 \(\upmu \) A. The overall system achieves efficiencies of 88% and 65% at Vin = 1.7 V and 2.2 V.