This work investigates a method to suppress the gate capacitance \(C_g\) as well as the ambipolar conduction \(I_{amb}\) of the Gate-Overlap Tunnel FETs (GOTFETs) while simultaneously improving their performance with appropriately engineered drain doping concentration and gate-overlap/underlap on the source/drain regions. We have optimized the device by studying the impact of material parameters, device structure, and dimensions on the performance in terms of the on current \(I_{on}\) , off current \(I_{off}\) , \(I_{on}\) : \(I_{off}\) ratio, inverse sub-threshold slope SS, gate-to-drain ( \(C_{gd}\) ), and gate-to-source ( \(C_{gs}\) ) capacitances. The proposed device performs better than the other TFETs reported earlier and the standard MOSFETs at the same technology node. The proposed Complementary GOTFET (CGOT) devices effectively reduce \(C_g\) ( \(\sim \) 1 fF/ \(\mu \) m) and \(I_{amb}\) ( \(\sim \) 0.1 pA/ \(\mu \) m) without compromising the high \(I_{on}\) ( \(\sim \) 1 mA/ \(\mu \) m), low \(I_{off}\) ( \(\sim \) 0.1 pA/ \(\mu \) m), and low SS ( \(\sim \) 26.79 mV/dec). We have used physics-based compact analytical models to support physical explanations. We have validated all the results reported in this work using extensive numerical simulations carried out with a precalibrated simulation setup. Finally, an investigation on the scaling trends reveals that the 7 nm CGOT devices outperform equally sized 7 nm industry-standard FinFETs.