In this paper, for the first time, we have proposed a new 8T SRAM cell design by employing junctionless field effect transistor (JLFET) and dopingless (DL) JLFET to enable the high-speed operation of SRAM cell. Overall, four configurations of 8T SRAM cell are studied by employing the different device structures in place of access transistor (AT). With the help of device–circuit co-simulation approach, the performance metrics of 8T SRAM cells such as read static noise margin (RSNM) and read delay are analyzed and compared with its conventional counterpart 6T SRAM cells at 15nm gate length. We found that DLJLFET-based 8T SRAM cell shows significant improvement in RSNM and read delay than conventional JLFET. Circuit Simulation results of 8T SRAM cell indicate that DLJLFET-based promising candidate to achieve improved performance and stability.