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This work highlights an optimized low-power Schmitt trigger circuit with parallel connected feedback \(\mathrm {\left( PF-ST \right) }\) . Different Schmitt trigger configurations and their performance have been studied. All the simulation work is performed by using Cadence virtuoso 45nm CMOS technology. The proposed circuit offers significant hysteresis width that can be used where the input signal has the presence of noise. We have also analyzed dynamic and leakage power dissipation, and propagation delay considering variations in temperature and supply voltage. The optimized design offers 0.207 \(\times \) , 0.180 \(\times \) , and 1.054 \(\times \) of dynamic and leakage power consumption and propagation delay less than conventional ST circuits. 2000 Monte Carlo simulation shows that our PF-ST has less effect on process variations.

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Parallel Feedback Controlled Low-Power and Reliable Schmitt Trigger Circuit

  • 会议论文

  • 发表日期：

    2025年

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  • Raveesh Khola,
  • Kaushal Kumar,
  • Nitesh Kumar Dhale,
  • Aryan Kannaujiya,
  • Ambika Prasad Shah

摘要

This work highlights an optimized low-power Schmitt trigger circuit with parallel connected feedback \(\mathrm {\left( PF-ST \right) }\) . Different Schmitt trigger configurations and their performance have been studied. All the simulation work is performed by using Cadence virtuoso 45nm CMOS technology. The proposed circuit offers significant hysteresis width that can be used where the input signal has the presence of noise. We have also analyzed dynamic and leakage power dissipation, and propagation delay considering variations in temperature and supply voltage. The optimized design offers 0.207 \(\times \) , 0.180 \(\times \) , and 1.054 \(\times \) of dynamic and leakage power consumption and propagation delay less than conventional ST circuits. 2000 Monte Carlo simulation shows that our PF-ST has less effect on process variations.