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In this work we proposed an In-Memory Computing (IMC)-based hamming code Parity Generator (Three bit XOR) and Check bit Generator (Four bit XOR) in 45 nm CMOS Technology. The key objective of this paper is to reduce the power consumption because of the data transfers that are being done from processor to memory and vice versa. The proposed work was compared with the conventional work (CMOS pull up and pull down Three bit XOR circuit). The power consumption is 2.08X less than the conventional. The delay is comparable in both the cases when RC data path delay modeled for 30 ps in conventional. In real time, data path varies more and IMC stands with less delay compared to it. Furthermore, energy consumption which is an important Figure of Merit (FoM) is 1.78 \(\times \) less than conventional Computing.

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Approach Toward In-Memory Computing-Based Hamming Code Implementation For Error Correction and Detection

  • 会议论文

  • 发表日期：

    2025年

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  • Vani Marani,
  • A. B. Chandrahas Reddy,
  • Soundrapandiyan Kavitha,
  • Bhupendra Singh Reniwal

摘要

In this work we proposed an In-Memory Computing (IMC)-based hamming code Parity Generator (Three bit XOR) and Check bit Generator (Four bit XOR) in 45 nm CMOS Technology. The key objective of this paper is to reduce the power consumption because of the data transfers that are being done from processor to memory and vice versa. The proposed work was compared with the conventional work (CMOS pull up and pull down Three bit XOR circuit). The power consumption is 2.08X less than the conventional. The delay is comparable in both the cases when RC data path delay modeled for 30 ps in conventional. In real time, data path varies more and IMC stands with less delay compared to it. Furthermore, energy consumption which is an important Figure of Merit (FoM) is 1.78 \(\times \) less than conventional Computing.