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The fabless nature of integrated circuit (IC) manufacturing process has made them vulnerable to covert and malicious modifications called Hardware Trojan Horses (HTH). The HTHs consist of trigger circuits that are activated on rare vectors, and use the payload circuit to inject the malicious signal upon activation. This paper proposes a test vector generation procedure that focuses on activating payload nets of any present HTH within the host IC. Various features of payload have been extracted from gate-level Trust-Hub circuits. Neural network classifier is utilised to flag the IC nets over the extracted payload features. Weighted random vectors have been generated with respect to the influence of primary inputs over the nets flagged by the neural model. Gaussian Mixture Model (GMM) is used on these vectors to generate test vector subset based on the impact of the vectors on the flagged nets. The generated test vector is seen to be significantly more compact and often sensitises payload nets within the tested gate-level Trust-Hub circuits.

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Test Vector Generation for Detecting Hardware Trojan Using Machine Learning Approaches

  • 会议论文

  • 发表日期：

    2025年

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  • Tapobrata Dhar,
  • Surajit Kumar Roy,
  • Chandan Giri

摘要

The fabless nature of integrated circuit (IC) manufacturing process has made them vulnerable to covert and malicious modifications called Hardware Trojan Horses (HTH). The HTHs consist of trigger circuits that are activated on rare vectors, and use the payload circuit to inject the malicious signal upon activation. This paper proposes a test vector generation procedure that focuses on activating payload nets of any present HTH within the host IC. Various features of payload have been extracted from gate-level Trust-Hub circuits. Neural network classifier is utilised to flag the IC nets over the extracted payload features. Weighted random vectors have been generated with respect to the influence of primary inputs over the nets flagged by the neural model. Gaussian Mixture Model (GMM) is used on these vectors to generate test vector subset based on the impact of the vectors on the flagged nets. The generated test vector is seen to be significantly more compact and often sensitises payload nets within the tested gate-level Trust-Hub circuits.