A rapid shift toward performance and energy efficient processors, combined with slower transistor scaling has paved the way for Domain Specific Architectures (DSA) in mainstream computing. The recent advent of an open and flexible ISA like RISC-V has further endorsed this change and provided the means to make DSA a reality. With Security and Safety being the forerunners in today’s DSA trends, one would find that most applications catering to these domains rely heavily on bit manipulation algorithms and can benefit significantly in performance with the presence of a Bit Manipulation Instruction set (BMI). Acknowledging the fact, this paper introduces a scalable and configurable framework that implements the ratified BMI extension of RISC-V. The implementation accounts for various optimization strategies and thereby gives the user a wider span of design-choices, to build a truly custom RISC-V core with BMI support. Results indicate that for a baseline operating frequency of 100MHz on an Artix-7 FPGA, the proposed work incurs an area overhead of only 20% on a tiny in-order RISC-V core while providing an average performance boost of 5.93% on standard EmbenchTM benchmarks.