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Brain computer interfaces (BCIs) system is based on signal acquisition and processing to control a computer or an external device. Electroencephalograms (EEG) signal is very effective for analysis of brain signals for diagnosis of neurological diseases. Compression of these signals is important for saving power and bandwidth in the novel application scenarios. Signal acquisition and feature extraction techniques are playing an important role in EEG signal processing. In this paper, a Very-Large-Scale Integration (VLSI) architecture of a 1-dimensional discrete wavelet transform (DWT) module for feature extraction from EEG signal processing in BCI application has been proposed. The proposed DWT architecture is simulated and synthesized in terms of slice, clock frequency, slice flip-flops, and delay. The field programmable gate array (FPGA) implementation of the proposed architecture shows the improvement in terms of area and delay compared to Exclusive OR (XOR)-Multiplexer (MUX) Adder-based DWT and Ripple Carry Adder (RCA)-Binary to Excess-1 Converter (BEC) Adder-based DWT architectures.

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An Efficient DWT Architecture for Feature Extraction from EEG Signal in BCI Applications

  • 会议论文

  • 发表日期：

    2026年

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  • Jhilam Jana,
  • Sayan Tripathi,
  • Jaydeb Bhaumik

摘要

Brain computer interfaces (BCIs) system is based on signal acquisition and processing to control a computer or an external device. Electroencephalograms (EEG) signal is very effective for analysis of brain signals for diagnosis of neurological diseases. Compression of these signals is important for saving power and bandwidth in the novel application scenarios. Signal acquisition and feature extraction techniques are playing an important role in EEG signal processing. In this paper, a Very-Large-Scale Integration (VLSI) architecture of a 1-dimensional discrete wavelet transform (DWT) module for feature extraction from EEG signal processing in BCI application has been proposed. The proposed DWT architecture is simulated and synthesized in terms of slice, clock frequency, slice flip-flops, and delay. The field programmable gate array (FPGA) implementation of the proposed architecture shows the improvement in terms of area and delay compared to Exclusive OR (XOR)-Multiplexer (MUX) Adder-based DWT and Ripple Carry Adder (RCA)-Binary to Excess-1 Converter (BEC) Adder-based DWT architectures.