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The design and simulation of a high-efficiency buck converter are presented, converting a 3.3 V input to a regulated 1.8 V output with a constant 0.5A current. The converter employs voltage mode control (VMC), a widely utilized control method in integrated circuits, and is implemented using UMC 180 nm CMOS technology. Simulation results indicate an efficiency exceeding 81% under specific load conditions. A practical design example illustrates the converter’s ability to maintain stable voltage and current outputs. The results highlight the effectiveness of VMC in achieving efficient buck converter design using 180 nm CMOS technology.

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Design and Implementation of a High Efficiency 3.3 V to 1.8 V Buck Converter in 180 nm CMOS

  • 会议论文

  • 发表日期：

    2025年

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  • Ravindra S. Radder,
  • Sujata S. Kotabagi,
  • Diven S. Bafna,
  • Lakshmishree Kattimani,
  • Manjula Benal

摘要

The design and simulation of a high-efficiency buck converter are presented, converting a 3.3 V input to a regulated 1.8 V output with a constant 0.5A current. The converter employs voltage mode control (VMC), a widely utilized control method in integrated circuits, and is implemented using UMC 180 nm CMOS technology. Simulation results indicate an efficiency exceeding 81% under specific load conditions. A practical design example illustrates the converter’s ability to maintain stable voltage and current outputs. The results highlight the effectiveness of VMC in achieving efficient buck converter design using 180 nm CMOS technology.