Accurate square-root computations on hardware are desired in vast array of applications including digital signal processing, image processing, robotics, etc. Through this paper, we propose a high-performance square root calculation algorithm that can compute the square root of a number in 8 clock cycles. The algorithm based on modified long division method has been implemented on Altera DE2 FPGA Development board, running at 50 GHz clock speed. The proposed architecture requires 160 ps for computation, which maps to 6.25 GHz maximum operating frequency. The design occupies 1238 logic elements and dissipates 118.83 mW total thermal power.