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With the rapid shrinking of technology nodes in the deep submicron era, the increasing power density in SRAM circuits has become a significant concern due to increased average power and leakage current. The SRAM is a vital component of cache memory in system on system on chip (SOC) designs, where it consumes a significant portion of power. This paper presents novel low power 16 nm SRAM cells design using 3 different architectures namely architecture-1 (A-1), architecture-2 (A-2), and architecture-3 (A-3) in CMOS technology and results are compared with conventional 6 T (C-6 T) SRAM cell. All the results are verified with the LTSPICE simulator. All the proposed SRAM cells design show improvements in terms of average operational and leakage power reduction, while A-1 additionally shows enhanced WSNM, and reduced WRITE delay as compared to the C-6 T SRAM cell. The proposed cell shows an improvement as compared with the published results and is suitable for high speed, low power memory circuit design in the VLSI industry.

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Novel Low Power SRAM Cells in 16 nm CMOS Technology

  • 会议论文

  • 发表日期：

    2026年

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  • Prakhar Chaturvedi,
  • Abhijit Asati

摘要

With the rapid shrinking of technology nodes in the deep submicron era, the increasing power density in SRAM circuits has become a significant concern due to increased average power and leakage current. The SRAM is a vital component of cache memory in system on system on chip (SOC) designs, where it consumes a significant portion of power. This paper presents novel low power 16 nm SRAM cells design using 3 different architectures namely architecture-1 (A-1), architecture-2 (A-2), and architecture-3 (A-3) in CMOS technology and results are compared with conventional 6 T (C-6 T) SRAM cell. All the results are verified with the LTSPICE simulator. All the proposed SRAM cells design show improvements in terms of average operational and leakage power reduction, while A-1 additionally shows enhanced WSNM, and reduced WRITE delay as compared to the C-6 T SRAM cell. The proposed cell shows an improvement as compared with the published results and is suitable for high speed, low power memory circuit design in the VLSI industry.