Differential Power Analysis (DPA) attacks pose a serious threat to cryptographic implementations, and this study offers innovative methods for building integrated circuits that are resistant to these attacks. We suggest a new Power balanced logic family to reduce the connections between data processing and power usage. A new balanced logic family that maintains constant power draw across various data patterns is introduced by our methodology. In comparison with traditional designs, experimental results on an AES cryptographic core built with 65 nm CMOS technology show resistance to power analysis attacks, with a 45.8% area overhead and a negligible performance impact. The approach requires no other design elements or operational constraints, making it suitable for implementation in practical settings.