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The following article simulates and investigates a Fault-Tolerant (FT)-based Arithmetic Logic Unit (ALU) with the help of parity preserving reversible logic design and Carbon Nanotube Field Effect Transistor (CNTFET) models. Parity Preserving Reversible Gates (PPRG) make the implemented ALU design more efficient, as it could operate even if an intermediate node fails. Also, it is energy efficient, as it has no information loss and it consumes less heat than a conventional design; as a result, it helps in power efficiency. The performance of the PPRG-based Full Adder and proposed ALU Design is validated using the CNTFET Verilog-A models at 32 nm technology with the Cadence Virtuoso tool. This simulated design has presented considerable power gains compared to previous designs.

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Design of Parity Preserving Reversible Design-Based Fault-Tolerant ALU on 32 nm CNTFET

  • 会议论文

  • 发表日期：

    2026年

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  • Anurag Chauhan,
  • Soumyajit Das

摘要

The following article simulates and investigates a Fault-Tolerant (FT)-based Arithmetic Logic Unit (ALU) with the help of parity preserving reversible logic design and Carbon Nanotube Field Effect Transistor (CNTFET) models. Parity Preserving Reversible Gates (PPRG) make the implemented ALU design more efficient, as it could operate even if an intermediate node fails. Also, it is energy efficient, as it has no information loss and it consumes less heat than a conventional design; as a result, it helps in power efficiency. The performance of the PPRG-based Full Adder and proposed ALU Design is validated using the CNTFET Verilog-A models at 32 nm technology with the Cadence Virtuoso tool. This simulated design has presented considerable power gains compared to previous designs.