RISC-V, a reduced instruction set computing (RISC) architecture, is rapidly gaining popularity within the embedded industry due to its open-source nature and adaptability. Unlike traditional proprietary architectures, RISC-V offers a flexible and modular design that supports customization to meet specific application requirements. This has led to an increasing shift from conventional architectures to open-source solutions, as developers seek enhanced control over core utilization and power consumption. One of the significant advantages of RISC-V is its capability to operate seamlessly on both FPGA systems and Linux environments, further broadening its application scope. Despite its growing popularity, there are currently limited stand-alone systems and CPUs that fully leverage the RISC-V instruction set architecture (ISA). In this chapter, we explore the design and implementation of a 32-bit RISC-V ISA with a five-stage pipeline on a Xilinx 7000 FPGA. The five-stage pipeline architecture consists of the following cycles: fetch, decode, execute, memory, and write-back. Implementing this architecture on the Xilinx 7000 FPGA demonstrates the effectiveness of utilizing RISC-V in FPGA-based systems. The Xilinx 7000 series, known for its high-performance logic cells and advanced configuration options, provide an ideal platform for showcasing the flexibility and power efficiency of RISC-V. This study also highlights how the open-source nature of RISC-V is encouraging the creation of custom extensions and optimizations. This implementation not only contributes to the growing body of knowledge surrounding RISC-V but also depicts its potential for optimizing power consumption and core utilization in embedded systems.