Power dissipation significantly impacts VLSI circuit performance and reliability. It increases temperature, shortens lifespans, and increases failure rates. High power dissipation also affects timing and efficiency, leading to timing errors and decreased performance. Power supply noise, a potential issue, can cause functional errors, reduced noise margins, and data corruption. This research proposes ECO, a novel approach that incorporates non-structural process variations, allowing for the development of high-performance chips without requiring significant redesign. Power noise analysis is crucial for proper circuit functionality and reliability. The new design shows a 6.76% improvement in total power consumption.