The prime aim of this study is to examine the temperature affectability on parasitic capacitance of the dual metal-double gate-tunnel FET (DMDG-TFET) with different source region material, i.e., Si0.5Ge0.5 and Si. To achieve this, the inherent capacitances such as gate-to-gate capacitance (Cgg), the gate-to-source capacitance (Cgs), and the gate-to-drain capacitance (Cgd) have been examined for different source materials and also at different ambient temperatures ranging from 200 to 400 K. The parasitic capacitances decide the intrinsic delay of the FET and subsequently the speed of the FET. The capacitive analysis reveals that Si0.5Ge0.5 is better than basic Si-based DMDG-TFET device. Further, the device shows great robustness under the wide temperature range.