Approximate computing is an emerging paradigm in computer architecture and digital design that leverages many applications’ inherent error tolerance to improve energy efficiency and performance significantly. This paper introduces highly optimal input rescheduling and approximate logic for 5-3 counters. The Wallace tree approach creates the 8 * 8 multiplier, which balances speed and area efficiency compared to other multiplier architectures. The error distance (ED) and the mean error distance (MED) are used to evaluate the approximate compressor multiplier. The proposed design, when employed in the pre-processing of DNN, especially in image processing, results in reduced error rate and optimized processing time. Finally, the multiplier is analyzed using 90-nm silicon technology in the mentor graphics tool to validate the area, power, and delay reports of the current 8 * 8 multiplier architecture. With the best multiplier, the image database is multiplied with a reduced CPU time of 6% less than true and 2 % an existing approximate multiplier. The multiplied database images are applied to a pre-trained deep learning network to evaluate a comparable accuracy report.