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Multiplier is a crucial factor influencing processor performance, making it’s optimization vital for efficient computing. This paper introduces a multiplier design that achieves remarkable improvements, reducing resource utilization by more than half, overall logic delay to nearly a quarter and total power consumption to less than a quarter of compared to conventional Radix-2 Booth’s multiplier. The proposed design was synthesized and implemented using Xilinx Vivado on a Zedboard FPGA, demonstrating its effectiveness and scalability for modern FPGA-based systems.

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Design of Resource, Delay and Power Efficient Single Cycle Signed Multiplier

  • 会议论文

  • 发表日期：

    2026年

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  • Hepin Gondaliya,
  • Parth Monpara,
  • Dhaval Shah

摘要

Multiplier is a crucial factor influencing processor performance, making it’s optimization vital for efficient computing. This paper introduces a multiplier design that achieves remarkable improvements, reducing resource utilization by more than half, overall logic delay to nearly a quarter and total power consumption to less than a quarter of compared to conventional Radix-2 Booth’s multiplier. The proposed design was synthesized and implemented using Xilinx Vivado on a Zedboard FPGA, demonstrating its effectiveness and scalability for modern FPGA-based systems.