Any computing system, from small digital systems to supercomputers, that consists of several processing units is based on arithmetic circuits, particularly the adders. The frequency of failures has increased due to the smaller size of electronic equipment. Therefore, creating circuits that are fault tolerant is crucial. The capacity of a system to recognize and recover from a malfunction is known as fault tolerance. Any design can boost system longevity and dependability by adding fault tolerant features, but doing so comes at the expense of more hardware. The cost and system performance must be well-balanced. For all critical applications, the system must automatically reconfigure itself so that it can continue to function normally even in the case of a malfunction, because the most important block in any digital architecture is the adder. This project compares the performance metrics, such as power and area, of parallel adders, carry save adders, carry select adders, and parallel prefix adders of various sizes (4, 8, and 16 bits) and their fault-tolerant architectures on the Xilinx Vivado platform.