Energy efficiency is becoming more critical in digital systems, especially in power-hungry arithmetic applications like image processing. Compact design is crucial in contemporary error-tolerant applications based on high-performance processor cores. Data processing subsystem topologies affect processor core performance. High quantity data computing Very Large Scale Integration (VLSI) architectures must reduce area, time, and power to achieve accuracy. Unique low-power adder and multiplier circuits for image processing are proposed in this paper. By reducing carry propagation, the adder reduces power consumption while retaining accuracy in the most crucial bits with approximation computing. The multiplier uses Wallace tree structure and partial product approximation to reduce sequential adds and power-hungry bit transitions. Both circuits also use clock gating, voltage scaling, and power gating to reduce dynamic and static power consumption. The suggested circuits are tested in a convolution, filtering, and pixel-wise image processing pipeline. Real-time applications in resource-constrained embedded systems can use the design due to its high throughput and accuracy and significant power savings.