Computational capacity of a system is constrained by the capabilities of its integrated circuits (ICs). In digital signal processing (DSP) systems, the time required to complete an operation depends on the multiplication factor, making a high-speed adder essential for optimal performance. In this paper a complete full adder and Vedic Multiplier is designed using novel quasi-resistance-based gate diffusion input technique (FQR-GDI). Because of this, fewer transistors are required in comparison to typical CMOS-based adder designs. The power consumption and latency of the circuit are greatly reduced by using the FQR-GDI technique. The threshold dips in the original GDI cell are eliminated, and the output signals are enhanced because of this approach. The TSMC library has been used to implement the suggested process in Tanner Tools.