Scholarlink

This paper examines the optimization of the Advanced Encryption Standard (AES) within the RISC-V architecture, emphasizing improved performance for secure computing in IoT devices and embedded systems. The study begins with a basic implementation of AES in C, which serves as the foundation for applying assembly-level optimizations to critical algorithm components such as SubBytes, InvSubBytes, ShiftRows, InvShiftRows, and AddRoundKey. A development environment was established, including configuring a RISC-V toolchain, the GNU Compiler Collection (GCC) for RISC-V, and the Spike simulator for instruction-level validation and performance analysis. Simulations ensured the accuracy of data transformations and adherence to RISC-V’s instruction execution principles. The assembly-optimized implementation was benchmarked against the standard C version, demonstrating significant system throughput and efficiency improvements. The study highlights the effectiveness of combining low-level programming with high-level logic to unlock the full potential of RISC-V’s open-source Instruction Set Architecture (ISA). These findings underline the critical role of low-level optimizations in enhancing cryptographic systems, particularly in environments requiring secure and efficient processing. The research concludes with a discussion on performance gains. It offers insights into future directions for advancing AES and other cryptographic algorithms, addressing modern technology’s growing demand for secure computing.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

The Design of Scalar AES Instruction Set Extensions for RISC-V Processor

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Chinmay Parmar,
  • Vijay Savani

摘要

This paper examines the optimization of the Advanced Encryption Standard (AES) within the RISC-V architecture, emphasizing improved performance for secure computing in IoT devices and embedded systems. The study begins with a basic implementation of AES in C, which serves as the foundation for applying assembly-level optimizations to critical algorithm components such as SubBytes, InvSubBytes, ShiftRows, InvShiftRows, and AddRoundKey. A development environment was established, including configuring a RISC-V toolchain, the GNU Compiler Collection (GCC) for RISC-V, and the Spike simulator for instruction-level validation and performance analysis. Simulations ensured the accuracy of data transformations and adherence to RISC-V’s instruction execution principles. The assembly-optimized implementation was benchmarked against the standard C version, demonstrating significant system throughput and efficiency improvements. The study highlights the effectiveness of combining low-level programming with high-level logic to unlock the full potential of RISC-V’s open-source Instruction Set Architecture (ISA). These findings underline the critical role of low-level optimizations in enhancing cryptographic systems, particularly in environments requiring secure and efficient processing. The research concludes with a discussion on performance gains. It offers insights into future directions for advancing AES and other cryptographic algorithms, addressing modern technology’s growing demand for secure computing.