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This chapter guides readers through designing a minimal single-cycle CPU supporting five LoongArch instructions: add.w, addi.w, ld.w, st.w, and bne. It explains datapath construction, control signal generation, and module integration (e.g., register file, ALU, RAM). The chapter details verification methods using test programs and FPGA-based debugging. Practical tasks involve building and testing a 5-instruction CPU and then expanding it to support 20 instructions.

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Design A Single-Cycle CPU

  • 章节

  • 发表日期：

    2025年

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  • Wenxiang Wang,
  • Jinzhang Xing

摘要

This chapter guides readers through designing a minimal single-cycle CPU supporting five LoongArch instructions: add.w, addi.w, ld.w, st.w, and bne. It explains datapath construction, control signal generation, and module integration (e.g., register file, ALU, RAM). The chapter details verification methods using test programs and FPGA-based debugging. Practical tasks involve building and testing a 5-instruction CPU and then expanding it to support 20 instructions.