In recent years, the demand for high-performance neural networks has surged due to advancements in artificial intelligence (AI) and machine learning applications. However, this increased computational demand has brought significant power consumption challenges, especially for edge devices. In this paper, we present a novel VLSI architecture designed to optimize both power efficiency and computational throughput for neural network acceleration. Our architecture leverages a combination of low-power design techniques, such as clock gating and voltage scaling, along with hardware-specific optimizations tailored for matrix multiplication, the most power-hungry operation in neural networks. We implemented our design using a 28 nm CMOS process and evaluated its performance on standard neural network benchmarks. The results show a significant reduction in power consumption by up to 40% compared to existing architectures, without compromising on computational accuracy or speed. This power-efficient VLSI solution offers a promising approach for enabling high-performance neural networks in power-constrained environments, such as mobile and embedded systems.