As a method for testing power Through-Silicon Vias (TSVs) in 3D-ICs, prior studies have proposed detecting open defects by measuring the resistance between power pads placed directly beneath the TSVs. However, optimizing the resistance measurement points and deriving the defect coverage for this test require repeated circuit simulations to calculate the resistance between power pads, which is time-consuming. To accelerate this process, this paper proposes a method to estimate defect coverage using sampling and optimize measurement points through Bayesian optimization. Numerical experiments demonstrated that the time required for defect coverage estimation was accelerated by a factor of 10 compared to methods without sampling. Additionally, the time needed to optimize measurement points was reduced by approximately 1.6 times compared to the conventional Exhaustive Neighborhood Search method when the approximate locations of the optimal measurement terminals were unknown.