As the demand for asymmetric encryption in embedded devices increases, the SM2 algorithm, which is based on elliptic curve cryptography, has been widely applied in fields such as secure communication and digital signatures. Nevertheless, the intricate computations involved in elliptic curve point multiplication and modular arithmetic present substantial challenges to the resource-constrained and computationally limited nature of embedded systems. This paper presents several optimizations for the specific curve used in the SM2 algorithm, including a multilevel Karatsuba-Ofman large-number multiplier design, an enhanced fast modular reduction algorithm, and precomputed addition chains to accelerate modular inversion. With these optimizations, we achieve a high-performance, low-resource SM2 implementation, completing point multiplication in approximately 27.3k clock cycles. The optimized design was implemented on three Xilinx FPGA platforms: Virtex-7, Kintex-7, and Artix-7, with latencies of 0.238 ms, 0.254 ms, and 0.281 ms, respectively, and a DSP unit consumption of only 81. Compared with traditional implementations, the latency was reduced by approximately 15-20%, and DSP resource consumption decreased by 43.75%. This design significantly reduces resource usage while ensuring high computational efficiency, making it suitable for resource-constrained embedded devices.

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Optimized Design and Implementation of the FPGA-Based SM2 Algorithm

  • Haidong Huang,
  • Juhao Hu,
  • Jing Wu,
  • Chengnian Long

摘要

As the demand for asymmetric encryption in embedded devices increases, the SM2 algorithm, which is based on elliptic curve cryptography, has been widely applied in fields such as secure communication and digital signatures. Nevertheless, the intricate computations involved in elliptic curve point multiplication and modular arithmetic present substantial challenges to the resource-constrained and computationally limited nature of embedded systems. This paper presents several optimizations for the specific curve used in the SM2 algorithm, including a multilevel Karatsuba-Ofman large-number multiplier design, an enhanced fast modular reduction algorithm, and precomputed addition chains to accelerate modular inversion. With these optimizations, we achieve a high-performance, low-resource SM2 implementation, completing point multiplication in approximately 27.3k clock cycles. The optimized design was implemented on three Xilinx FPGA platforms: Virtex-7, Kintex-7, and Artix-7, with latencies of 0.238 ms, 0.254 ms, and 0.281 ms, respectively, and a DSP unit consumption of only 81. Compared with traditional implementations, the latency was reduced by approximately 15-20%, and DSP resource consumption decreased by 43.75%. This design significantly reduces resource usage while ensuring high computational efficiency, making it suitable for resource-constrained embedded devices.