BPSK is a subsystem module used in digital transmission and complex computations technique in digital communication systems. The BPSK digital system is designed using a reversible logic gate which yields in minimal power consumptions in data path modules such as multiplexer. The MUF reversible logic gate is designed to develop multiplexer architecture, which are digitally modeled in the subsystem of digital communication systems. The design architectures are synthesized in gate level using Register Transfer Level (RTL) compiler in 65 nm technology node. In this paper, we made a comparison between reversible and optimized architectures. The proposed optimized architecture reduces average power consumption.