Scholarlink

This paper presents a digital computing-in-memory (CIM) SRAM that can effectively execute small to medium size various-bit precision quantized neural networks. This design uses dynamic logic to compute the bitwise multiplication to reduce area overhead and achieve high performance. The design can be reconfigured to support various bit precision multiply-and-accumulate (MAC) operations in a bit serial manner. The bit cell array consists of 32 computing sections and each section has an independent bit sum and accumulate unit in order to make the utilization more efficient when executing small MAC operations. By adopting the foundry provided push rule 8T SRAM bit cell, the design achieves a compact area and high stability. This design is implemented in 40 nm CMOS technology. The simulation result shows that this design achieves a maximum area efficiency of 9985 GOPS/mm2 and a maximum energy efficiency of 122 TOPS/W. Furthermore, taking MobileNet as an example, this design demonstrates much higher utilization compared with other state-of-the-art SRAM CIM macros.

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A High-Utilization Reconfigurable Digital Computing-in-Memory SRAM Using Dynamic Logic for Edge Neural Network Applications

  • 会议论文

  • 发表日期：

    2025年

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  • Xiangguang Su,
  • Yangzhan Mai

摘要

This paper presents a digital computing-in-memory (CIM) SRAM that can effectively execute small to medium size various-bit precision quantized neural networks. This design uses dynamic logic to compute the bitwise multiplication to reduce area overhead and achieve high performance. The design can be reconfigured to support various bit precision multiply-and-accumulate (MAC) operations in a bit serial manner. The bit cell array consists of 32 computing sections and each section has an independent bit sum and accumulate unit in order to make the utilization more efficient when executing small MAC operations. By adopting the foundry provided push rule 8T SRAM bit cell, the design achieves a compact area and high stability. This design is implemented in 40 nm CMOS technology. The simulation result shows that this design achieves a maximum area efficiency of 9985 GOPS/mm2 and a maximum energy efficiency of 122 TOPS/W. Furthermore, taking MobileNet as an example, this design demonstrates much higher utilization compared with other state-of-the-art SRAM CIM macros.