The current work proposes an innovative design for a 9 T CMOS SRAM device to increase stability and lower power usage. To ensure the operation of our suggested 9 T SRAM circuit, we compared our results with previously available data. The suggested cell has similar metrics to the intended 9 T SRAM cell, which uses the same design ideas and technology. The recommended cell's stability was assessed using N-curve measurements. The recommended 9 T SRAM cell conducts write operations via bit line (BL) charging and discharging, resulting in reduced power usage. When compared to normal SRAM cells, the proposed SRAM circuitry requires at least 92% less reading power. Furthermore, the recommended SRAM's write power usage was reduced by a minimum of 97% as compared to standard SRAM designs. The recommended SRAM unit reduces reading time by at least 63% when compared to existing SRAM cells. In addition, power consumption during data writing to the specified SRAM was lowered by at least 96% when compared to traditional architectures.