The Dadda multiplier represents an enhancement over the Wallace tree multiplier, which typically features many adders, uneven critical paths, and a complex layout for multiplication. The Dadda method significantly reduces propagation delays and power consumption by leveraging a more streamlined architecture that minimizes the number of adders required. This report details the development of a complete adder module distinct from the conventional designs, which predominantly utilize XOR gates. The proposed full adder design incorporates fewer transistors, optimizing hardware deployment and area utilization. CMOS technology is employed in constructing full and half adder blocks to further enhance power efficiency and reduce propagation lags. The development of the model is facilitated using FPGA and Cadence, showcasing its capability in creating low-power, high-performance 16-bit multiplication applications.