Clock jitter is very important for satellite data transmission performance. Based on the Gauss distributing and the requirement of sampling setup time and hold time, this study accomplished the model of data transmission performance affected by sampling clock jitter. The simulation analysis results show that with the intensification of clock jitter and the increase of sampling frequency, the BER decreases rapidly, the offset between the sampling clock phase and the data will further deteriorate the system’s performance, which match the experiments well. Methods such as canceling the clock cache and isolating the external clocks have been proposed, which have played a good role in controlling clock jitter and improving the system performance. To ensure the application of the research, the above model analysis methods, simulation analysis, experimental verification results, and design improvement are extracted and formed into knowledge points. The achievement is valuable for directing the satellite data transmission system design.