While short-circuit detection technology for SiC MOSFETs has reached the nanosecond range, ongoing research continues to focus on achieving even faster response times. A more rapid short-circuit protection mechanism can reduce the extent of Safe Operating Area (SOA) violations, thereby mitigating device degradation and prolonging operational lifespan. Equally critical is the reliability of the short-circuit detection signal, which serves as a key performance indicator. Parameter shifts within the device and oscillations induced by parasitic parameters are primary contributors to detection failure or false triggering. To address these challenges, this paper presents an optimized short-circuit detection method based on gate charge, leveraging the dynamic characteristics of the Miller capacitance under short-circuit conditions. The proposed method achieves detection times of 25 ns for HSF and 36 ns for FUL, and can reliably adapt to changes in temperature, power levels, and stray inductance. A behavioral model is developed to provide circuit design guidelines adaptable to various power devices, and the method’s feasibility is verified through simulation.