This Verilog design implements reversible adders, essential for reversible computing paradigms like quantum computing. The design comprises two main modules: RevAdder and RevAdd16. RevAdder is a 4-bit reversible adder utilizing Peres and Fredkin gates to compute the sum and carry-out. RevAdd16 extends this functionality to 16-bit addition by instantiating four RevAdder modules and managing carry signals between them. The design emphasizes reversibility, enabling computations to be undone perfectly, and demonstrates the use of generative techniques for efficient modular design. Overall, these modules provide foundational components for reversible computing architectures, offering potential benefits in energy efficiency and computation reversibility; by implementing the method as discussed in this paper, it showed a significant improvement of 63.8% of quantum cost, 40% of garbage output, and 62.3% delay over existing method.