Scholarlink

In today's fast-paced world, where new technologies emerge every day, concerns about data security and privacy are more important than ever. Cryptographic algorithms are essential tools for protecting sensitive information. In this paper, we present a secure, energy-efficient method for data protection using hardware-based solutions. We implement the Advanced Encryption Standard (AES) algorithm on a Spartan-7 Field Programmable Gate Array (FPGA) to achieve this goal. To reduce power consumption, we apply a technique that involves adjusting the output load capacitance. Our results reveal that as the capacitance increases, the power consumption of the hardware also rises. Specifically, we observed a 13.55% increase in total power consumption when the capacitance was increased from 5 to 50 pF.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Low-Power AES Design on Spartan-7 FPGA via Output Load Capacitance Scaling

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Keshav Kumar,
  • Chinnaiyan Ramasubramanian,
  • Bishwajeet Pandey

摘要

In today's fast-paced world, where new technologies emerge every day, concerns about data security and privacy are more important than ever. Cryptographic algorithms are essential tools for protecting sensitive information. In this paper, we present a secure, energy-efficient method for data protection using hardware-based solutions. We implement the Advanced Encryption Standard (AES) algorithm on a Spartan-7 Field Programmable Gate Array (FPGA) to achieve this goal. To reduce power consumption, we apply a technique that involves adjusting the output load capacitance. Our results reveal that as the capacitance increases, the power consumption of the hardware also rises. Specifically, we observed a 13.55% increase in total power consumption when the capacitance was increased from 5 to 50 pF.