Phase Locked Loop (PLL) has undergone considerable advancements, transitioning from larger CMOS (Complementary Metal Oxide Semiconductor) nodes to smaller FinFET technologies. These developments have driven improvements in power efficiency, chip area and frequency adaptability for a range of applications, particularly in communications. In this paper, a comprehensive survey of PLL designs is presented, analysing the technological and architectural progress that has led to enhanced performance capabilities. Trade-offs between phase noise and power consumption are examined, alongside the increased design complexities associated with advanced PLL configurations such as Fractional-N, mmWave and injection-locked architectures. The paper also explores current challenges, including minimizing transistor counts, achieving ultra-low power operation and extending stability at high frequencies. This survey underscores the critical role of ongoing innovation in PLL design to meet the evolving requirements of next-generation electronic systems.