Optimizing XOR Gate Designs for Low-Power Hearing Aid Circuits Across Different Technology Nodes and Voltage Sources
摘要
This research explores the optimization of XOR gate designs for use in adder and multiplier circuits within hearing aids. Investigating various transistor counts ranging from 3 to 15, the study evaluates the performance of MOSFET-based XOR gates across two technology nodes (130 and 90 nm) and two voltage sources (0.7 and 1.2 V). Notably, Uma Sharma’s FGMOS XOR design, featuring only 3 transistors, proves ideal for low-voltage applications at 0.7 V, exhibiting a minimal Power-Delay Product (PDP) of 0.00015aJ. Conversely, at 1.2 V, M. Augirre-Hernandez’s Pass Transistor Logic (PTL) XOR circuit, with 12 transistors, achieves a minimal PDP of 0.07 aJ, closely followed by H. Naseri’s PTL-based XOR circuit at 0.09 aJ. These findings provide crucial insights into the nuanced selection of XOR gate designs tailored to specific voltage requirements, advancing the efficiency and performance of hearing aid circuits.