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A modified speed-efficient and low power 4-bit carry look ahead adder (CLA) is proposed in this work. To reduce delay of the circuit, GDI technique has been employed to design the basic gates used in the CLA architecture. The circuit has been implemented in LTspice 16.3 using 180 nm CMOS technology. In the proposed circuit, the delay is found to be 0.001 ns, power is 255μWatt and power delay product (PDP) is 0. 255 × 10−15 Ws. Also, the proposed design is compared with existing ones and has been found better and efficient in terms of performance parameters like signal-delay, area and power.

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A High Speed 4-bit Carry Look Ahead Adder Using GDI Technique in 180 nm Technology

  • 会议论文

  • 发表日期：

    2025年

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  • Barsha Barman,
  • Nabanita Das,
  • Malvika,
  • Vivek Kumar,
  • Kavicharan Mummaneni

摘要

A modified speed-efficient and low power 4-bit carry look ahead adder (CLA) is proposed in this work. To reduce delay of the circuit, GDI technique has been employed to design the basic gates used in the CLA architecture. The circuit has been implemented in LTspice 16.3 using 180 nm CMOS technology. In the proposed circuit, the delay is found to be 0.001 ns, power is 255μWatt and power delay product (PDP) is 0. 255 × 10−15 Ws. Also, the proposed design is compared with existing ones and has been found better and efficient in terms of performance parameters like signal-delay, area and power.