Scholarlink

In our paper, we investigate the memristor-based full-adder using implication logic. It covers the comparison of mathematical models and finds the lower computational steps for designing one-bit full-adder. The proposed model is more reliable and energy efficient. We have proposed an adder using CMOS and memristor. Further, we design inverting and non-inverting operational amplifiers with a memristor. The ALU design using a memristor is 40.13% efficient and the area consumed is 15% less in comparison to CMOS technology. An AND gate with memristor-based model is more efficient in area (75%) and delay and power consumption (98%). Inverting and non-inverting operational amplifier CMOS are better in performance as compared with existing circuits. The proposed circuits show lower power consumption as compared to existing systems.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

An Efficient Implementation of Hybrid Memristor-CMOS-Based Adder Architecture for Low Power Applications

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Harshal J. Kotadiya,
  • Mandar Jatkar,
  • Sudhir Rai

摘要

In our paper, we investigate the memristor-based full-adder using implication logic. It covers the comparison of mathematical models and finds the lower computational steps for designing one-bit full-adder. The proposed model is more reliable and energy efficient. We have proposed an adder using CMOS and memristor. Further, we design inverting and non-inverting operational amplifiers with a memristor. The ALU design using a memristor is 40.13% efficient and the area consumed is 15% less in comparison to CMOS technology. An AND gate with memristor-based model is more efficient in area (75%) and delay and power consumption (98%). Inverting and non-inverting operational amplifier CMOS are better in performance as compared with existing circuits. The proposed circuits show lower power consumption as compared to existing systems.